The EtherCAT IP cores for Altera®, AMD®, Microchip®, and Lattice® FPGAs enable the implementation of the EtherCAT slave communication function within an FPGA. The EtherCAT functionality – such as the number of FMMUs and SYNC managers, the size of the DPRAM, and so on – can be configured to meet the requirements. Different license variants are offered.
For the master implementation, developers have the Master Sample Code (ET9200), the EtherCAT Slave Stack Code (ET9300), and the EtherCAT configurator (ET9000) at their disposal. The latter exports a network description file (ENI – EtherCAT Network Information) from the device description files (ESI – EtherCAT Slave Information) of the connected devices.
The required conformity tests for slave devices can be performed in-house with the EtherCAT Conformance Test Tool (CTT). The advanced FSoE Conformance Test Tool (FSoE CTT) is suitable for the conformity testing of slave and master devices for Safety over EtherCAT (FSoE) (ET9402, ET9403).
- Reset all filter values
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